● Overview

This board is intended to be used by customers to implement and design 10G Ethernet systems based on transceiver host boards that support XAUI interfaces. This mezzanine card is intended to be part of an openly sold Development Kit and can be bundled with packages of Software and IP Cores. It will have 2 full duplex 10G SFP+ channels with a XAUI backend interface. The XAUI to SFP+ HSMC provides a hardware platform for developing embedded systems based on XAUI based Altera “GX” based devices. The devices that presently support XAUI are Arria GX, Arria II GX, Stratix II GX and Stratix IV GX.

● Specification

• Features

  • Two independent XAUI interfaces from the HSMC to the BCM8727
  • Two independent SFI interfaces from the BCM8727 to SFP+ cages
  • MDIO interfaces
  • I2C EEPROM for HSMC identification and user data
  • Si5334C clock generator
  • 156.25MHz reference available on SMA connectors and through the HSMC connector
  • 4 user bi-color LEDS for each channel (8 total bi-color LEDs)

  Block Diagram

  

  Connectivity

  

  DUAL XAUI TO SFP+ HSMC BOARD connects to the Startix IV GX FPGA Development Board

  

  DUAL XAUI TO SFP+ HSMC BOARD connects to the Altera DE4 FPGA Development Board

● Layout

• Size：126*78mm

● Resources

Documents

Title	Version	Size(KB)	Date Added	Download
DUAL_XUAI_UserManual	-	1968	2011-05-04

Please note that all the source codes are provided "as is". For further support or modification, please contact Terasic Support and your request will be transferred to Terasic Design Service.
More resources about IP and Dev. Kit are available on Altera User Forums.

• 10-Gbps Ethernet MAC and XAUI PHY Interoperability Hardware Demonstration Reference Design http://www.altera.com/literature/an/AN638.pdf

• Altera's 10G Ethernet (XAUI) Solution
  http://www.altera.com/technology/high_speed/protocols/10gb_ethernet/pro-10gb_ethernet.html