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▶ Overview

The DE25-Nano is a next-generation FPGA development board that brings Agilex™ 5 performance into the palm of your hand. Building upon the widespread adoption of the DE10-Nano, the DE25-Nano upgrades nearly every dimension: from a 138K-LE Agilex™ 5 FPGA, onboard 2GB LPDDR4, and USB-Blaster III, to an enhanced dual-cluster ARM Cortex-A76/A55 HPS architecture — all while maintaining the same compact form factor. Whether you're developing AI models, vision pipelines, or control systems, the DE25-Nano offers a modern hardware foundation for real-time processing at the edge.

What truly sets the DE25-Nano apart is its versatile I/O and production-ready architecture — with support for HDMI, MIPI, ADC, GPIO, and shared HPS/FPGA memory. This makes it not only a powerful dev kit for rapid prototyping, but also a reliable hardware platform ready to be adopted in real-world applications — from embedded vision, robotics to signal processing and edge analytics. Paired with Terasic’s rich ecosystem of daughter cards, the DE25-Nano enables fast iteration and scalable deployment across industries — bridging the gap between development and production, education and enterprise.

Partnerships

LPDDR4 SDRAM Memory Solution

Clock Solution

Power, Logic, Level Translator and USB Type-C solution

DE25-Nano

• FPGA: A5EB013BB23BE4SCS (138K Logic Elements)
• Dimensions: 106.9 mm x 68.58mm
• Onboard Programmer: USB-Blaster III via USB Type-C connector
• Configuration Mode: Supports ASx4 mode with 128 Mbit QSPI Flash
• Cooling Solution: Active heatsink

FPGA side

• LPDDR4:1GB LPDDR4 with 32-bit data bus. Data Rate: 2666 MT/s (Rev. B) / 2133 MT/s (Rev. A)
• SDRAM:128MB SDRAM with 16-bit data bus
• HDMI Output: Supports up to 1080p resolution
• Camera Interface: One MIPI connector with 2 data lanes
• ADC: 8-channel ADC with 2×5 header
• GPIO Headers: Two 3.3V 2×20 DE-GPIO headers
• User Interface: 8 user LEDs, 2 buttons, 4 slide switches
• UART Port: 2-pin UART via Type-C connector
• Thermal Management: Integrated temperature sensor and fan controller

HPS side

• MicroSD Socket
• LPDDR4 Memory: 1 GB LPDDR4 with 32-bit data bus (shared with FPGA). Data Rate: 2133 MT/s.
• Ethernet: Gigabit Ethernet PHY with RJ45 port
• USB Port: One USB 2.0 port via Type-C connector
• UART Interface: UART to USB via Type-C connector
• Sensor: Integrated accelerometer
• User Interface: 1 LED, 1 button, and 1 cold reset button

Software Support

• FPGA Example Code
• Linux BSP

Block Diagram

Connection to 2x20 GPIO Daugher Card

• Connect to LT24
  
   
• Connect to MTL2
  
   
• Connect to D8M
  
   
• Connect to SMK
  
   
• Connect toRFS2
  

▶ Layout

Board Size:

How to Find the DE25-Nano Development Kit Revision?

Documents

Title	Version	Size	Date	Download
Build Linux image from scratch			2025-11-26
DE25-Nano User Manual (revB)	1.1	5,432(KB)	2025-11-10
DE25-Nano User Manual (revA)	1.0	4,884(KB)	2025-09-23

Resource Packages

Title	Version	Size	Date	Download
DE25-Nano Resource Package (revB)	1.0.0		2025-11-10
DE25-Nano Resource Package (revA)	1.0.0		2025-09-23

Linux BSP (Board Support Package): MicroSD Card Image

Title	Version	Size	Date	Download
Linux Console (Ubuntu 22.04.3 + Kernel 6.12.11-lts; rev. A/B Hardware)	1.1.0		2025-10-07

Please note that all the source codes are provided "as-is". For further support or modification, please contact Terasic Support and your request will be transferred to Terasic Design Service.

More resources about IP and Dev. Kit are available on FPGA User Forums.

Quartus Support

Included with DE25-Nano Development and Education Kit is a free license for Quartus® Pro Edition software — no additional license purchase is required. Developers can leverage full design and compilation capabilities of Quartus Pro without incurring licensing fees. Learn more about acquiring your free license.

1. DE25-Nano Board
2. Acrylic (Installed)
3. Active Heatsink (installed)
4. 5V/4A Power Supply
5. USB Type-C Cable
6. MicroSD Card (Installed)
7. Quick Start Guide