▶ Product Description

The AXW49 development board utilizes the AMD Zynq UltraScale+ RFSoC Gen3 XCZU49DR FPGA as its core processor. It features 16-channel 14-bit ADC ports with a maximum sampling rate of 2.5 GSPS and 16-channel 14-bit DAC ports with a maximum sampling rate of 9.85 GSPS. This configuration simplifies the RF signal chain, maximizes I/O channel density without bandwidth compromise, and leverages heterogeneous processing capabilities (combining FPGA logic with quad-core APUs and dual RPUs) to reduce power consumption. High-speed connectors extend functionality for AD/DA clocks, HDIO (High-Density I/O), MIO (Multiplexed I/O), and GTY/GTR transceiver buses (e.g., via QSFP28 optical ports and NVMe interface), with flexible IO voltage control supporting multiple levels (1.8V, 3.3V) across different banks.

Supporting large-scale MIMO radio, 5G baseband, fixed wireless access, and cable access in communication applications; testing and measurement as well as satellite communication, and similar high-performance RF scenarios.

▶ Applications

• ● Wireless access (5G/LTE, FWA)

• ● Cable access (broadband/data services)

• ● Test and measurement

• ● Radar signal processing

• ● Satellite communication

• ● Other RF-intensive applications

▶ Key Features

• ● AMD/Xilinx Zynq™ Ultrascale+™ RFSoC Gen3 ZU49DR:
  ◆ 930K Logic Cells
  ◆ 16 x 14bit 2.5 GSPS RF-ADC
  ◆ 16 x 14 bit 9.85GSPS RF-DAC
  ◆ ARM® quad-core Cortex™-A53 up to 1.33GHz
  ◆ ARM® dual-core Cortex™-R5F up to 533MHz
  ◆ 16nm FinFET+ FPGA fabric● 4GB DDR4 SDRAM on PS
  ● 4GB DDR4 SDRAM on PL
  ● 256 MB QSPI Flash
  ● 2 x QSFP28 Optical (100G)
  ● RF SMBs
  ◆ 16 x 14bit RF-ADC @ 2.5 GSPS
  ◆ 16 x 14bit RF-DAC @ 9.85 GSPS
• ● 1 x M.2 Interface
  ● 1 x USB 3.0 Port
  ● 3 x Gigabit Ethernet
  ● 1 x JTAG
  ● 1 x Micro SD
  ● EEPROM: 4-Kbit I2C Serial EEPROM
  ● 4 x LED
  ● 32x IO
  ● 12V single supply
  ● Dimensions: 200 x 200 mm form factor

▶ Specifications

▶ What's Inside

▶ Product Selection Matrix

Product Matrix

▶ Documentations and Data