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Embedded System Design on SoC FPGA
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        [ΰ]
  ǰ : IPG000617319
       : Inipro
 IP :
 DE1-SoC Kit :
  :
  :
  


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: ̺ S 705ȣ ̳

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: ̴ (ũ )
2017-06-15 ~ 2017-06-16
2017-09-14 ~ 2017-09-15
2017-12-14 ~ 2017-12-15

ð : 09:30 ~ 17:30 (17ð, 2 14ð, ߽, , )

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ݰ꼭 帳ϴ.
īÿ ݰ꼭 ȵ˴ϴ.
ڼݰ꼭 ڵ纻 , ó, ̸ּҸ
̴ ̸(webmaster@inipro.net) Ǵ ѽ(02-2047-1049) ֽñ ٶϴ.



Intel Soc FPGA ϵھ Dual Cortex-A9 μ Peripheral, interconnectȸΰ FPGA MCU+FPGA ؾ ߴ ý one-chipȭ ִ ÷Դϴ. , Intel Ǹ ° ̺귯 մϴ. ؼ Intel SoC FPGA Ȱ ִ پ Ͻ ֽϴ.


Intel SoC FPGA
Intel SoC FPGA Ȱϱ


SoC FPGA ϰ ϰ ϰ Ͻô .
SoC FPGA ȰϿ ý 踦 ϰ Ͻô .


Verilog Design using Vivado or VHDL Design using Vivado
C α׷
ũμ

& ϵ


Intel Quartus Prime Lite Edition
DE1-SoC Kit


Ͽ մϴ.


1 - SoC FPGA Ұ

- SoC FPGA
- FPGA Design Flow
- HPS Design

̷ 50%
ǽ 50%

2 - SoC FPGA

- HPS-FPGA Design
- QT Ȱ GUI
- OpenCL ȯ Ұ ¾

̷ 50%
ǽ 50%

ô


8ȣ 4 ⱸ ø 1 Ǿ ֽϴ.
̺ θ ̺ մϴ.






 ݾ 90,000 ̸̻ ۵˴ϴ.

  ִ ǰ ֹ Ϸ 3 ȿ ۵˴ϴ.

 Ϲ ǰ ֹ Ϸ 5~10 ȿ ۵˴ϴ.
ǰ ǻ Ʒ ó ֽñ ٶϴ.

 ֹ ǰ ȯұ Ʒ ϴ.
  • ܼ ɿ ֹҴ Ұմϴ.
  • ǰÿ ǰ ǰ ¿  ǸŰ 쿡 ǰ մϴ.
  • ǰ ǰ ¿ ־ ǸŰ Ұ ¿ ߰ ߻ ֽϴ.
  • ǰ Ϸκ ǰϱ Ⱓ ȯұݾ Ʒ ϴ.
    • ֹ : ȯұݾ = ǰ - ؿܿ۷
    • 7̳ : ȯұݾ = ǰ - ؿܿ۷ - ޼ ( 5,000 )
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