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Nexys4 DDR
Nexys4 DDR Artix-7 FPGA Board
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  ǰ : IPG000616866
       : Digilent
 IP :
 ó :
Nexys 4 DDR Pmod Pack
Verilog HDL Design using Vivado
Verilog HDL Design using ISE

VHDL Design using Vivado
VHDL Design using ISE


The Nexys 4 DDR is a drop-in replacement for our cellular RAM-based Nexys boards. Featuring the same Artix-7 field programmable gate array (FPGA) from Xilinx, the Nexys 4 DDR is a ready-to-use digital circuit development platform designed to bring additional industry applications into the classroom environment. The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more resources than earlier designs. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C) and collection of USB, Ethernet, and other ports, the Nexys 4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, a temperature sensor, MEMs digital microphone, speaker amplifier and plenty of I/O devices allow the Nexys 4 DDR to be used for a wide range of designs without needing any other components. The most notable improvement is the replacement of the 16 MiB CellularRAM with a 128 MiB DDR2 SDRAM memory. Digilent will provide a VHDL reference module that wraps the complexity of a DDR2 controller and is backwards compatible with the asynchronous SRAM interface of the CellularRAM, with certain limitations.

The Nexys 4 DDR is compatible with Xilinx's new high-performance Vivado Design Suite as well as the ISE toolset, which includes ChipScope and EDK. Xilinx offers free WebPACK versions of these toolsets, so designs can be implemented at no additional cost.

Support Materials

Datasheet (PDF) Schematics (PDF)

For all other material:

Resource Center


Processor/IC: Xilinx Artix-7 FPGA XC7A100T-1CSG324C


  • UART/JTAG USB port
  • Pmod for XADC signals
  • Audio connector
  • Ethernet connector
  • USB host connector
  • microSD card connector
  • 12-bit VGA output
  • Four Pmod ports
  • Power jack

Programming: Vivado Design Suite as well as the ISE toolset


  • Xilinx Artix-7 FPGA XC7A100T-1CSG324C
  • 15,850 logic slices, each with four 6-input LUTs and 8 flip-flops
  • 4,860 Kbits of fast block RAM
  • Six clock management tiles, each with phase-locked loop (PLL)
  • 240 DSP slices
  • Internal clock speeds exceeding 450 MHz
  • On-chip analog-to-digital converter (XADC)
  • 128 MiB DDR2
  • Serial Flash
  • Digilent USB-JTAG port for FPGA programming and communication
  • microSD card connector
  • Ships with rugged plastic case and USB cable
  • USB-UART Bridge
  • 10/100 Ethernet PHY
  • PWM audio output
  • 3-axis accelerometer
  • 16 user switches
  • 16 user LEDs
  • Two tri-color LEDs
  • PDM microphone
  • Temperature sensor
  • Two 4-digit 7-segment displays
  • USB HID Host for mice, keyboards and memory sticks
  • Pmod for XADC signals
  • 12-bit VGA output
  • Four Pmod ports


  • Nexys 4 DDR Artix-7 FPGA
  • Digilent custom hardshell plastic case with protective foam
  • Micro USB cable

Welcome to the resource center for the Nexys 4 DDR!

Here you will find all the reference materials that Digilent has created for this board, as well as links to any external content we have tracked down. If you are interested in purchasing the Nexys 4 DDR, visit the product page on our main website: Nexys 4 DDR


  • Sell SheetPDF
  • SchematicPDF
    • PDF Schematic of the PCB generated by Altium
  • Reference ManualWiki PDF
    • Technical description of the Nexys 4 DDR and all of its features. The Wiki page may contain more up-to-date information than the PDF.
  • Migration GuideWiki
    • This guide describes how to migrate a project that targets the Nexys 2, Nexys 3, or Nexys 4 to the Nexys 4 DDR

Design Resources

  • Vivado Board FilesWiki
    • Installing the 7-Series Vivado Board Files allows you to create Vivado projects that directly target the Nexys4-DDR hardware
  • Master XDCZIP
    • This file defines the pin constraints for every device on the Nexys 4 DDR for Vivado designs.
  • Master UCFZIP
    • This file defines the pin constraints for every device on the Nexys4-DDR for ISE designs.
  • Xilinx Memory Interface Generator (MIG) ProjectZIP
    • This package contains the files needed to properly configure a Xilinx MIG component so that it works with the onboard DDR.
  • SRAM to DDR ComponentWiki
    • This component can be dropped into designs to provide an easy to use SRAM-like interface to the DDR2. The interface is similar to the asynchronous interface of the CellRAM on previous Nexys boards.


  • Getting Started GuideWiki
    • Great starting point for new Nexys 4 DDR owners. Includes the kit contents, instructions for running the out of box demo, and instructions for building a simple design.
  • Nexys 4 DDR Programming GuideWiki
    • This guide walks through the different methods available for programming the FPGA on the Nexys 4 DDR
  • Getting Started with MicroBlazeWiki
    • Follow this introduction on how to get started with Microblaze using Vivado IP Integrator.
  • Getting Started with MicroBlaze ServersWiki
    • Follow this tutorial on how to get an echo server running with MicroBlaze using Vivado IP generator.

Reference Projects

  • General I/O DemoWiki
    • Basic demo that uses the onboard switches, buttons, LEDs, and UART
  • Advanced I/O DemoWiki
    • This demo is loaded in the QSPI flash at the factory. This complex design uses nearly every peripheral device on the Nexys 4 DDR
  • VGA Test Pattern with Mouse OverlayWiki
    • This project generates a test pattern on the VGA port and also displays a pointer that can be controlled with a mouse attached to the USB-HID port
  • Keyboard controllerWiki
    • This demo outputs keyboard scan codes to the 7-segment display when buttons are pressed on a keyboard attached to the USB-HID port.
  • XADC DemoWiki
    • Basic demo that shows a simple implementation with the Artix-7 XADC
  • Music Looper DemoWiki
    • This project uses the XADC to read audio data and save it into DDR. The program then loops the audio and allows the user to record multiple tracks on top of each other.
  • Audio Spectrum DemoWiki
    • This project uses the Onboard microphone and the fft IP block to implement a visual of the audio data.

* Test Project from China Teamwiki

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