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Verilog HDL Design
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790,000
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690,000
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990,000
Embedded System Design on Zynq
20,000
Verilog HDL Design using Vivado
12,000
Verilog HDL Design using Quartus
12,000
Verilog HDL Design using ISE
12,000
VHDL Design using Vivado
12,000
VHDL Design using Quartus
12,000
VHDL Design using ISE
12,000

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Socket Design Service
High Performance Socket ߿뿪
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߿뿪 ó


TEL : 02-2047-1048
Mail : polo@inipro.net




 ݾ 90,000 ̸̻ ۵˴ϴ.

  ִ ǰ ֹ Ϸ 3 ȿ ۵˴ϴ.

 Ϲ ǰ ֹ Ϸ 5~10 ȿ ۵˴ϴ.
ǰ ǻ Ʒ ó ֽñ ٶϴ.

 ֹ ǰ ȯұ Ʒ ϴ.
  • ܼ ɿ ֹҴ Ұմϴ.
  • ǰÿ ǰ ǰ ¿  ǸŰ 쿡 ǰ մϴ.
  • ǰ ǰ ¿ ־ ǸŰ Ұ ¿ ߰ ߻ ֽϴ.
  • ǰ Ϸκ ǰϱ Ⱓ ȯұݾ Ʒ ϴ.
    • ֹ : ȯұݾ = ǰ - ؿܿ۷
    • 7̳ : ȯұݾ = ǰ - ؿܿ۷ - ޼ ( 5,000 )
    • 7 ~ 30 : ȯұݾ = ǰ - ǰ10% - ؿܿ۷ - ޼ ( 5,000 )
    • 30 ~ 60 : ȯұݾ = ǰ - ǰ30% - ؿܿ۷ - ޼ ( 5,000 )
    • 60 ~ 90 : ȯұݾ = ǰ - ǰ50% - ؿܿ۷ - ޼ ( 5,000 )
    • 90 ~ 120 : ȯұݾ = ǰ - ǰ70% - ؿܿ۷ - ޼ ( 5,000 )
    • 120 ~ 150 : ȯұݾ = ǰ - ǰ90% - ؿܿ۷ - ޼ ( 5,000 )
 TEL : 02-2047-1047 , E-Mail : webmaster@inipro.net



 ̴ο ̴ ī ϰ ֽϴ.

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