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Verilog HDL Design using Vivado
790,000
Verilog HDL Design using Quartus
790,000
VHDL Design using Vivado
790,000
VHDL Design using Quartus
790,000
Verilog HDL Design
790,000
Embedded System Design on Zynq
690,000
Embedded Linux on Zynq
990,000

3,000,000
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Verilog HDL Design using Vivado
790,000
Verilog HDL Design using Quartus
790,000
VHDL Design using Vivado
790,000
VHDL Design using Quartus
790,000
Embedded System Design on Zynq
690,000
Embedded Linux on Zynq
990,000


ҹ


: ϴ ( Ϳ 1 1PC ʿմϴ.)

:

ð :

ο : 10 (10 ʰ 1 ߰ 10) 

û


û : ֹ Ϸ Ͻø ˴ϴ.

ݰ꼭 帳ϴ.
īÿ ݰ꼭 ȵ˴ϴ.
ڼݰ꼭 ڵ纻 , ó, ̸ּҸ
̴ ̸(webmaster@inipro.net) Ǵ ѽ(02-2047-1049) ֽñ ٶϴ.

û


Verilog HDL Design using Vivado (Verilog Vivado)

Verilog HDL Design using Quartus (Verilog Quartus)

VHDL Design using Vivado (VHDL Vivado)

VHDL Design using Quartus (VHDL Quartus)

Embedded System Design on Zynq (Zynq Design)

Embedded Linux on Zynq (Zynq Linux)

& ŰƮ


Xilinx Vivado HL WebPACK Edition or Intel Quartus
Zybo Kit or DE1-Soc Kit ( ŰƮ )





 ݾ 90,000 ̸̻ ۵˴ϴ.

  ִ ǰ ֹ Ϸ 3 ȿ ۵˴ϴ.

 Ϲ ǰ ֹ Ϸ 5~10 ȿ ۵˴ϴ.
ǰ ǻ Ʒ ó ֽñ ٶϴ.

 ֹ ǰ ȯұ Ʒ ϴ.
  • ܼ ɿ ֹҴ Ұմϴ.
  • ǰÿ ǰ ǰ ¿  ǸŰ 쿡 ǰ մϴ.
  • ǰ ǰ ¿ ־ ǸŰ Ұ ¿ ߰ ߻ ֽϴ.
  • ǰ Ϸκ ǰϱ Ⱓ ȯұݾ Ʒ ϴ.
    • ֹ : ȯұݾ = ǰ - ؿܿ۷
    • 7̳ : ȯұݾ = ǰ - ؿܿ۷ - ޼ ( 5,000 )
    • 7 ~ 30 : ȯұݾ = ǰ - ǰ10% - ؿܿ۷ - ޼ ( 5,000 )
    • 30 ~ 60 : ȯұݾ = ǰ - ǰ30% - ؿܿ۷ - ޼ ( 5,000 )
    • 60 ~ 90 : ȯұݾ = ǰ - ǰ50% - ؿܿ۷ - ޼ ( 5,000 )
    • 90 ~ 120 : ȯұݾ = ǰ - ǰ70% - ؿܿ۷ - ޼ ( 5,000 )
    • 120 ~ 150 : ȯұݾ = ǰ - ǰ90% - ؿܿ۷ - ޼ ( 5,000 )
 TEL : 02-2047-1047 , E-Mail : webmaster@inipro.net



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